Dynamic Cache Way Allocation for Power Reduction キャッシュ連想度の動的変更による消費電力削減 2004 年 1 月 30

The architects and circuit designers are increasingly care about the power aspect of microprocessors. The larger amount of built-in hardware is, the higher power the processors likely consume. Low power consumption is highly required not only for the processors driven by batteries but also for the powerful desktop or server processors whose the power budgets that over 100 Watts are not so uncommon. Our research focus on reducing power consumption in caches. Caches usually occupy a considerable portion of hardware resources. Optimizing caches for low power consumption is therefore important. In this thesis, we propose way-variable caches. A way-variable cache is a multiway set-associative cache where some of its cache ways can be disabled, depending on runtime cache demand of applications. Dynamic power is reduced by avoiding unnecessary switching activity in the disabled cache ways. Sleep transistors are added in the cache way circuits. Deactivating these transistors in disabled cache ways effectively suppresses the leakage currents, leading to reduction of static power. We also propose an original resizing algorithm that dynamically varies the number of enabled cache ways of the way-variable caches. By utilizing the information that is available in caches with LRU replacement algorithm, the resizing algorithm can quantitatively predict how much miss-rate increase as more cache ways are disabled. Disabling of cache ways then takes place as long as the predicted miss-rate increase is small. Evaluations are done via simulating a superscalar processor, having 16 KB, fourway set-associative instruction cache and data caches. Applications of way-variable caches to L1 instruction and data caches are considered in the evaluations. The evaluation results show that on average 1.83 ways out of four ways of the wayvariable instruction cache can be disabled with only 1.3% performance degradation. The values are 1.5 ways and 1.1% in the case of the way-variable data cache.